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FAQ
List of Questions
1.Questions frequently asked regarding FIFO
- What is "FIFO"?
- What is the difference from DRAM?
- What is the difference between FIFO and FRAM?
- What is the product lineup?
- In what fields is FIFO used?
- What are the advantages of using FIFO?
- What are the differences between the MSM51x221 type and the MSM51x222 type?
- What are the differences between the MSM548331, the MSM548332 and the MSM548333?
- Why should a read address and a write address be different?
- What is the read data when the address difference is 600 or more or 119 or less?
- What is the read data when the address difference is between 120 and 599?
- What are the read address and write address values after power is turned on?
- Is refresh required?
Answers
1.Questions frequently asked regarding FIFO
[Answer]
FIFO stands for "First-In First-Out". The FIFO write addresses always start with "0" and are sequentially assigned an increasing number such as "1", "2", "3", .... Therefore, it means First-Address-Data-In. Likewise, the read addresses also start with "0" and are sequentially assigned an increasing number such as "1", "2", "3".... Therefore, it means First-Address-Data-Out. Since the data written in the addresses starting with the address "0" is output sequentially starting with the address "0", this operation is called "First-In First-Out". FIFO and field memories store TV signals as digital data in field units for various signal/image processing. The basic function of a field memory is the FIFO (First-In/First-Out) operation. Basically in this function, the data input first is read first.
[Question]
What is the difference from DRAM?
[Answer]
Since FIFO is a serial-access memory, direct external input of complicated addresses is not required unlike DRAMs. As an address control method, only reset is available and addresses are counted using the clock input count. FIFO is made in a dual port configuration where input and output are independent from each other, allowing high-speed read and write processings independently and asynchronously. OKI's FIFO is designed based on a DRAM, but since a built-in self refresh circuit is used, external refresh operation is not required.
[Question]
What is the difference between FIFO and FRAM?
[Answer]
OKI sells two types of field memories, FIFO type and FRAM type. The difference is attributed to whether internal data is managed by a one-dimensional address or two-dimensional address. Originally, TV images are two-dimensional (X, Y); but are converted to one-dimensional (time: t) signals for signal processing. To store TV signals as one-dimensional signals, FIFO is suitable as it manages data as one-dimensional data. On the other hand, when data is managed as two-dimensional data such as camera-shake prevention circuits, scan converters, picture-in-picture, FRAM is suitable.
[Question]
What is the product lineup?
[Answer]
Depending on the data width and memory capacity, OKI provides FIFOs ranging from 1Mb to 10Mb and FRAMs of 3Mb/6Mb. One of the features is high-speed processing achieved by the cycle time of 12ns at the minimum.
Refer to the list of OKI's field image (FIFO) memories for details. Since a wide range of products are provided, we are sure that
you can find a suitable memory you require.
[Question]
In what fields is FIFO used?
[Answer]
The most popular application is temporary storage of TV signals.
- Three-dimensional Y/C separation circuits
- Picture-in-picture
- Frame synchronizers
- Digital video editors
- Scan converters
- Video capture
- Video cameras
- Electronic still cameras
- LCD monitors and plasma displays
A scan converter is a device to convert images having entirely different pixel count structures. for instance, a scan converter is used when displaying the images of a personal computer on a TV set.
A time-based collector is a device to allow smooth fetching of images with entirely different control frequencies into an image system.
[Question]
What are the advantages of using FIFO?
[Answer]
TV signals are continuous signals in the time direction. Since the address control corresponding to such signals is performed in a FIFO chip, the addresses need not be controlled externally. Therefore, control circuits can be simplified.
Since read processing and write processing can be executed independently in one memory, read/write timings need not be taken into consideration. Therefore, control circuits can be simplified.
[Question]
What are the differences between the MSM51x221 type and the MSM51x222 type?
[Answer]
To facilitate cascade connection, the input data fetching timing is delayed by 1 clock in the memory of the MSM514222 and the MSM518222 compared with the MSM514221 and the MSM518221. In cascade connection, the memories are connected in series and controlled with a common control signal, not with an independent control signal provided for each memory. Cascade connection enables the use of a memory as the one with double capacity.
[Question]
What are the differences between the MSM548331, the MSM548332 and the MSM548333?
[Answer]
1. The MSM548331 is a Line-by-Line type field memory of 768 pixels x 290 lines x 12-bit configuration. Memory access starts at the input of a line address and line addresses can be specified in line units. The write mask function and output data control are possible.
2. The MSM548332 has a 960 pixels x 290 lines x 12-bit configuration. The functions are exactly the same as those for the MSM548331. The difference is just in the pixel count.
3. The MSM548333 has a 768 pixels x 313 lines x 12-bit configuration as a whole, but to allow the operation in Y/C separation mode, 768 pixels x 313 lines x 8-bit configuration for the Y area and 768 pixels x 313 lines x 4-bit configuration for the C area are available.
Memory access starts at the input of a line address and a word address. The addresses can be specified in line units and in word units. This memory consists of three ports; one input port and two output ports. At the two output ports, different lines can be accessed separately. The write mask function is available, but output data control cannot be performed.
The features are summarized as follows:
- Functionally, the MSM548331 and the MSM548332 are the same.
The MSM548333 consists of 1 input port and 2 output ports, while the MSM748331 and the MSM548332 consist of 1 input port and 1 output port. - The MSM548333 supports both line addressing and word addressing, while the MSM548331 and the MSM548332 support line addressing only.
[Question]
Why should a read address and a write address be different?
[Answer]
DRAM is used for the memory array. To allow independent, high-speed, asynchronous input/output operation, read and write data are temporarily saved in the read and write registers, respectively. Data is automatically transferred between the registers and the memory array in the memory. Due to the difference between the read address and the write address, read operations are classified into 2 processings; reading the data before transferred (old data read) and reading the data after transferred (new data read).
Therefore, you should pay attention the difference between the read address and the write address when new data is definitely needed and when old data is definitely needed. Refer to the data sheet of each FIFO for details.
[Question]
What is the read data when the address difference is 600 or more or 119 or less?
[Answer]
When the difference between the read address and the write address is 600 or more or 262,262 or less, new data is output. When the difference is between 0 and 119, old data is output. (These address differences are for the MS51421/2/3. Refer to the notes in the data sheet for other memories.)
[Question]
What is the read data when the address difference is between 120 and 599?
[Answer]
When the difference between the read address and the write address is between 120 and 599 or 262214 or more, it is not guaranteed whether the output data is new data or old data. In this case, write data is written correctly. (These address differences are for the MS51421/2/3. Refer to the notes in the data sheet for other memories.)
[Question]
What are the read address and write address values after power is turned on?
[Answer]
After power is turned on, both the write address pointer and the read address pointer are undefined. Therefore, execute initialization of each pointer by performing resetting with RSTW and RSTR.
For details, refer to the notes in the data sheet.
[Question]
Is refresh required?
[Answer]
The FIFO is provided with a built-in self-refresh circuit so that external refresh operation is not required.
Some of DRAM, SDRAM, SGRAM, and Rambus also have a self-refresh function. However, self-refreshing is set by the external control in such memories and the memories cannot be accessed during self-refreshing. Since the FIFO starts self-refreshing fully automatically, no external control is required, enabling accesses anytime during internal refreshing.
