Oki ADI board is a standard JTAG ARM Debugger interface board. ADI stands for ARM Debugger Interface. Oki ADI board is very similar to ARM Multi ICE and its design is intended as a low priced, qualified replacement for ARM Multi ICE in a debugging configuration.
Oki ADI board requires the Oki ICE server to communicate with an RDI compatible debugger on the development host. Oki ICE is a communication server similar to ARM Multi ICE server. Oki ICE is bundled with Oki ADI boards. Oki ADI board is currently supported only for Windows 98 and Windows 95 systems. Currently there is no support for Windows NT or Windows 2000. Due to this compatibility issue, Oki no longer supports ADI boards.

ML674000 CPU board is shipped with a complete set of driver software for all of its peripherals. In addition, there are startup and Interrupt routines that can initialize the board. Memory Controller initialization routines and flash programming utilities are also included. Once the customer receives the board, they can readily load the bundled software into their software development tools and execute them. There is also a Software User's Manual that can help the user get started. The bundled software have been developed for various software development tools, including but not limited to ARM SDT 2.51, ARM ADS 1.2, and ARM Realview Developer's Kit for Oki. To run the software in other third party development tools, minor modifications of source code may be necessary.

ML674000 CPU board has the following memory configuration:

The example programs bundled with Oki's ML674K CPU-boards generally do not require ARM Semihosting to be enabled. In some cases, having Semihosting enabled will interfere with the performance of the sample software. As a rule, any sample program that uses the init.s module, does not require semihosting.
Although, the flash utility that is provided for ML674000 CPU-board requires Semihosting to be enabled and it will not function properly without it.
To disable semihosting in ARM debuggers, select Debugger Internals and set the semihosting_enabled variable to 0x00.

Problem Description: When interfacing to an ML67Q4003 CPU-board using standard JTAG-debugger interface units, JTAG errors are observed and as a result a JTAG connection cannot be established. Errors such as "JTAG not initialized" or "Could not stop processor" are noted. These errors may arise even though the user has been able to successfully connect via the same JTAG debugger interface unit to other Oki CPU-boards.

Solution:
The early versions of ML67Q4003 CPU-boards use an adaptive clocking circuit to synchronize the JTAG port. This JTAG circuit design is different from previous implementations on Oki ARM CPU-boards.

To be able to interface to ML67Q4003 CPU-board through JTAG, the user must configure their JTAG-Debugger Interface Unit (e.g. MultiICE) to use adaptive clocking.

Adaptive clocking is the method to synchronize all JTAG operations on a single clock edge. This may be necessary for various types of applications. In JTAG operation, the JTAG clock (TCK) is supplied by the JTAG-debugger interface unit. When adaptive clocking is utilized, the JTAG-debugger interface unit will issue a JTAG clock (TCK) and check for a return clock (RTCK) from the ARM MCU before issuing the next clock tick (TCK).

This concept is very useful in interfacing to systems which have widely varying clock frequencies. For example, in battery-operated operations, the application may utilize the flexible clock gears of ML674K MCUs to vary processor clock frequency based on processing needs of the system. In this type of application where the core clock frequency may frequently vary, the JTAG clock can be several times faster than the core frequency. Thus, adaptive clocking is used and insures that the JTAG-debugger interface unit adapts its clock frequency to the target system.

The figure below illustrates how the clocking circuit for the JTAG embedded-ICE of ML67Q4003 has been modified to generate the RTCK adaptive return clock (interfacing buffers are not shown).

Therefore, to interface to ML67Q4003 CPU-boards, the user has the following options:

If the JTAG-debugger interface unit at hand does not support adaptive clocking:

The ML67Q4002/3, ML67Q5002/3 Serial Flash Write utility supports using both the Hyperterm and Teraterm setups.

In ML674000, ML674001/2/3 and ML675001/2/3 MCUs, some of the PIO pins are multiplexed with SDRAM bank control signals. At any one time, these pins can be used as either PIOs or SDRAM control pins.

The role of these multiplexed functions is determined by external pin settings on the MCU. In ML674000, this role is set by input levels at the Mode[0:3] pins. In ML674001/2/3 and ML675001/2/3 MCUs, this setting is made by input level at the DRAME_N pin.

If the above noted external pins configure the DRAM block as enabled, then the particular GPIO pins multiplexed with the DRAM control signals can no longer be used and GPIOs and they only operate as DRAM signals. If these external pins disable the DRAM function, then the GPIO pins multiplexed with the DRAM signals will operate as PIO pins.

Operating systems such as Windows CE and Linux require a Memory Management Unit (MMU) to run. ARM7TDMI cores do not have a built in MMU. Therefore Windows CE is not supported on them.

There are versions of Embedded Linux that can run on micros without an MMU. One such popular version of Linux is uCLinux. For more information on this refer to www.lineo.com

In the ARM world, generally ARM cores that have the name ARMX2XTxxx, the 2 designates MMU capability and thus support for operating systems such as Linux and Windows CE. For example ARM920T or ARM720T have MMUs.

The Mode[0:2] pins of the processor handle the enabling and disabling of the DRAM controller and A-to-D converter of the processor. By disabling these hardware blocks through hardware, the power source to these blocks is cut off and hence power consumption of the ARM processor will drop significantly.

Mode[0:2] pins are also tied to additional functionalities such as enabling and disabling the Primary and Secondary functions of Processor pins.

To be able to access the flash, you need to first set the PIOA[10:14] to their secondary functions which are XA[19:23]. This is due to the fact that the chip is connected to these high address pins. To do this, you will need to set the Port Function Select Register (GPCTL=0xB7000000). Simply write a '1' to the 2nd bit (GPCTL2) of this register.

The GPIO pins of ML674000 are multiplexed with secondary functionalities. Thus, they can be configured and used either in their primary function as GPIOs or as their secondary functions. These settings are generally made in the Port Function Select Register (GPCTL). The Port B GPIOs PIOB[15:9] are an exception. These pins have a secondary function as SDRAM control pins.

To configure PIOB[15:9] for their primary function as GPIOs, the Mode[2:0] external pins of the MCU must be configured in hardware as noted in Chapter 4 "Chip Configuration" of ML674000 User's Manual. Based on the Mode[2:0] pin levels, the PIOB[15:9] pins will function in either their primary function as GPIO pins or their secondary function as SDRAM control pins.

The I/O cells of the UARTs of Oki ML674K/5K series are capable of handling data rates in excess of 512 Kbps. However, the maximum data rate depends on the performance of the application software running on the MCU. In other words, how fast can the application software respond to requests from the UART, and what other events does the application software have to respond to at the same time of servicing the UART. If the application software is burdened with responding to other events such as interrupts from other peripherals or processing other information, it may not be able to service the high data rate demands of the UART.

In sample trials carried out at room temperature, Oki engineers have been able to transmit and receive at transmission rates in excess of 512 Kbps on the 16550 UART peripheral of ML674K and ML675K ML674K/5K series. The SIO port of Oki's ML674K ML674K/5K series generally has a lower data rate performance due to the fact that it does not have buffers. Thus it is more prone to line errors.

In conclusion, data rates of up to 512 Kbps are possible on the ML674K/5K series UART. Users should evaluate the maximum data rate possible in their application based on their own application software and application demands on the MCU.