ASIC IP (Mega Macrocells)

Oki's system level design services support ASIC and SOC designs using industry leading Digital and Analog IP cores developed in-house and from third-party IP houses.  All IPs offered by OKI are silicon proven.

 

Digital IPs

Bus Interface

Description		Compatibility	Format		Technology
			Hard Macro	Soft Macro	0.13µm	0.15µm	0.22µm	0.35µm	0.5µm
USB 1.1 Host Controller		USB V 1.1
USB 1.1 Device Controller		USB v 1.1
USB 1.1 Device Controller with AMBA/APB Wrapper		USB v 1.1
USB 1.1 Transceiver		USB v 1.1
USB 2.0 Device Controller		USB v 2.0
USB 2.0 Device Controller with AMBA/AHB Wrapper		USB v 2.0
USB2.0 PHY		USB v 2.0
PCI Controller (33 MHz, 32 & 64bit)		PCI v 2.2
PCI Transceiver (66 MHz)		PCI v 2.3
PCI-X Transceiver (133 MHz)		PCI-X 1.1b
I²C Controller		I²C v 2.1
I²S Controller
Serial Peripheral Interface		SPI
CAN Controller		2.0B active
PCMCIA Card Controller with UART
800Mbps LVDS		IEEE 1596.3
622Mbps LVDS
166 MHz SSTL-2

Drawn geometries (effective geometries are smaller). Technologies: dual-, triple-, quad-, and five-layer metal

Communication

Description		Compatibility	Format		Technology
			Hard Macro	Soft Macro	0.13µm	0.15µm	0.22µm	0.35µm	0.5µm
UART with FIFO		16C550
		16C750
10 / 100 Ethernet MAC (W110)		IEEE 802.3x
10 / 100 Ethernet MAC with AMBA/AHB Wrapper		IEEE 802.3x
Gigabit Ethernet MAC (Z1000)		IEEE 802.3z

Drawn geometries (effective geometries are smaller). Technologies: dual-, triple-, quad-, and five-layer metal

Consumer

Description		Compatibility	Format		Technology
			Hard Macro	Soft Macro	0.13µm	0.15µm	0.22µm	0.35µm	0.5µm
Viterbi Decoder		IEEE 802.11a
Reed-Solomon Codec
Bit Elastic
Display Control Unit (LCD Controller)
NTSC/PAL Encoder (Logic portion only, not including DAC)
3DES
AES

Drawn geometries (effective geometries are smaller). Technologies: dual-, triple-, quad-, and five-layer metal

Storage

Description		Compatibility	Format		Technology
			Hard Macro	Soft Macro	0.13µm	0.15µm	0.22µm	0.35µm	0.5µm
SD Card Host Controller
Secure Digital I/O Card Interface
Memory Stick Host Controller
IDE Controller, ATAPI-5

Drawn geometries (effective geometries are smaller). Technologies: dual-, triple-, quad-, and five-layer metal

Microprocessor

Description		Compatibility	Format		Technology
			Hard Macro	Soft Macro	0.13µm	0.15µm	0.22µm	0.35µm	0.5µm
ARM7TDMI 32-bit RISC CPU		ARM7TDMI
ARM946E-88 32-bit RISC CPU (8K + 8K cache)		ARM946ES
ARM926EJS 32-bit RISC CPU		ARM920T

Drawn geometries (effective geometries are smaller). Technologies: dual-, triple-, quad-, and five-layer metal

Peripherals

Description		Compatibility	Format		Technology
			Hard Macro	Soft Macro	0.13µm	0.15µm	0.22µm	0.35µm	0.5µm
Direct Memory Access Controller
Real Time Clock		RTC
External Interrupt Controller

Drawn geometries (effective geometries are smaller). Technologies: dual-, triple-, quad-, and five-layer metal

 

Analog IPs

Analog/Mixed Mode

Description		Compatibility	Format		Technology
			Hard Macro	Soft Macro	0.13µm	0.15µm	0.22µm	0.35µm	0.5µm
25 MHz to 500 MHz PLL
12.5 MHz to 200 MHz PLL
SSCG PLL
3.3V to 2.5V Regulator
3.3V to 1.5V Regulator
3.3V to 1.2V Regulator

Drawn geometries (effective geometries are smaller). Technologies: dual-, triple-, quad-, and five-layer metal

 

ADC / DAC

Description		Compatibility	Format		Technology
			Hard Macro	Soft Macro	0.13µm	0.15µm	0.22µm	0.35µm	0.5µm
10 bit 8 Channel 400KHz ADC		C ladder - SAR
10 bit 40MHz ADC		Pipe Line (single input)
10 bit 40MHz ADC		Pipe Line (differential input)
12 bit 400KHz ADC		C ladder - SAR
10 bit 2 Channel 40MHz ADC		Pipe Line (differential input)
12 bit 400KHz ADC		C ladder - SAR
10 bit 40Msps ADC
12 bit 400Ksps ADC
10 bit 200KHz DAC		R - 4R
10 bit 1 Channel 100MHz DAC		Current Matrix (Differential Output)
10 bit 2 Channel 100MHz DAC		Current Matrix (Differential Output)
10 bit 3 Channel 50MHz DAC		Current Matrix (Single Output)
12 bit 110Mhz DAC		Current Matrix (Differential Output)
10 bit 200Khz DAC		C ladder - SAR
10 bit 2 Channel 100Mhz DAC		Current Matrix (Differential Output)
10 bit 3 Channel 100Mhz DAC		Current Matrix (Single Output)
10 bit 40Msps DAC		IEEE 1596.3
10 bit 100Msps DAC

Drawn geometries (effective geometries are smaller). Technologies: dual-, triple-, quad-, and five-layer metal