Extensive macrocell library including
- Phase locked loops (PLLs)
- High density single- and dual-port RAM
up to 600MHz (generated with RTISAN™
or VIRAGE™ RAM compiler)
- Real-time clock
- JTAG boundery scan
- Large IP database including: Ethernet 10/100
MAC, 1-Gigabit Ethernet MAC, ARM920T,
ARM7TDMI, ARM946E-S, ARM926EJ-S (32bit
RISC CPU), IEEE1394 (Firewire), UART (with
FIFO), USB 1.0 Device Controller, USB 2.0
Device Controller
- Most IPs are available with AMBA Wrapper
Multiple options for testability
- Scan, JTAG, BIST
- Automatic test pattern generation with scan
flip-flop macrocells, obtaining fault coverage
in excess to 95% (using TetraMax™)
- Support of automated scan insertion by
Synopsys DFT™
Flexible mixed 3/5 V operations
- Core Voltage: 3.3 /5V operation in 0.5 µm
(1st generation & 2nd generation), 3.3 V
operation in 0.35 µm, 2.5 V operation in
0.25 µm, 2.5 V operation in 0.22 µm,
1.5 V operation in 0.15 µm, 1.2V operation
in 0.13µm
- I/O Voltage: 3.3 V / 5 V operation in 0.5µm
(1st generation), 3.3 V operation in 0.5µm
(2nd generation), 3.3 V operation in 0.35 µm,
3.3 V operation in 0.25 µm, 3.3 V operation in
0.22 µm, 3.3 V operation in 0.15 µm, 3.3 V
operation in 0.13µm
Flexible VSS/VDD pin locations
Programmable output currents of
2, 4, 8, 16 and 24mA
Configurable I/O cells
- Output Macrocells: push pull, 3-state, open
drain, slew-rate-controlled output options
- Input Macrocells: Input-Buffer LVTTL/LVCMOS
levels, Input-Buffer LVTTL/LVCMOS Schmitt
levels, pull-up resistor and pull-down resistor
- Bi-directional Macrocells: I/O Buffer LVTTL/
LVCMOS input levels, I/O Buffer LVTTL/LVCMOS
Schmitt input levels
- Oscillator: low and medium-frequency
oscillator
Clock-tree macrocells with clock skew
guaranteed to be = 0.5 ns (for 0.5 µ
products) with a fan-out of = 9000 at
75MHz
Support of a wide range of design
tools including Synopsys™, Cadence
VerilogXL™, ModelSim™ etc.
10 prototypes included in NRE, up to
500 prototypes possible at initial build
and risc production option
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